Integrated circuits are, in broad terms, manufactured by processing a front side of an integrated circuit wafer comprising a multitude of integrated circuit dies or discrete power transistors or capacitors. The individual integrated circuits are then sawed from the wafer and mounted in an integrated circuit package, the connectors on the die are bonded to respective connectors on the package and the package is then sealed and ready for shipping.
One way of attaching a circuit die to a package is by soldering the backside of the die to a flange of the package. Mounting of the die in the package comprises specific problems when the integrated circuit is a power device, since such devices produce a significant amount of heat and therefore are exposed to thermal mismatch and stress. When the die, solder and flange expand or contract differently due to the cooling after soldering or generated heat, delamination can occur if the induced stress is too large, thereby ruining the device. It is thus important that the die, solder, flange, window frame and lead frame react approximately the same to a change in temperature, that is, has approximately similar coefficient of thermal expansion (CTE). Obviously the size of the die is of great importance since a larger die will experience larger thermal mismatch and stress for the same temperature. Thus, for large dies thermal mismatch can be a problem, when the die is a power device, such as RF power transistors.
It is also important that the die, solder and flange can dissipate the generated heat, that is, that the die, solder and flange are good thermal conductors. The better heat is dissipated through the solder and flange, the better the chip will operate and thus it is possible to reduce junction temperature and avoid so-called hotspots. It is necessary to thin the die as much as possible because the semiconductors, in general, are poorer thermal conductors than the solder and the flange. Since power devices also generate large currents, and that these currents will, at least for some designs, go through the solder and flange, it is also important that the solder and flange have as low resistivity as possible.
It is of course not possible to completely avoid thermal mismatching and stress since devices consisting of different material should be attached to each other. Therefore it is important that the die is attached to the flange with such strength that the attachment can withstand the stress induced by the thermal mismatch without impairing the quality of the connection between the die and the flange with respect to thermal and electric conductivity. One great factor affecting the thermal conduction and hotspots on the die is formation of voids in the solder.
Standard ceramic packages, flanges and ceramic window frames for power devices consists of CuW, having 80-90 weight percent wolfram and uses an AuSi eutectic alloy to achieve rather good thermal matching, see table 1. The attachment of the die is conventionally performed by an AuSi eutectic die-attach, which unfortunately oftentimes causes sever void problems with a large die. The AuSi eutectic die-attach can moreover induce strong stress on the die, which limits the size and thickness of the die. Thinner die is desirable since better heat conduction from the die to the solder and flange is achieved.
The CuW flanges have inferior thermal conductivity and is more expensive compared to CuZr flanges, with Zr=0.1 weight percent, Olin 151™. The CTE for CuZr flanges matches the CTE for AuSn, which could be used as solder. AuSn further has superior thermal and electrical conductivity and compared to AuSi. Furthermore, a lower soldering temperature can be used with the AuSn solder compared to the AuSi eutectic alloy. This will reduce the induced stress.
It should be noted that even if CuZr is primarily discussed in this specification other type of heat sink materials with better thermal conductivity than CuW, could be used, specifically materials using powder metallurgy such as PCM or CPC. PCM stands for Powder Copper Molybdenum, with 30-40 weight % Cu infiltration onto the powder Mo, and CPC stands for Copper-PCM-Copper and is a laminate of copper and PCM and copper. The layers are clad under heat and pressure by rolling to form the CPC with certain thickness combinations, for example CPC(141), CPC(232), where the number stands for the thickness proportion between the different layers. Even a pure Copper heat sink is applicable, however the CuZr alloy is more stable with respect to mechanical and electrical properties than the pure copper.
Thus, it seems obvious to use CuZr as flange and AuSn as solder. However, it has hitherto been impossible to find a method for producing strong adhesion using AuSn for larger dies and for power devices, at least partly due to formation of voids and/or delamination between the die and solder where the greatest thermal mismatch and interface instability occur, see table 1.
TABLE 1Comparison between AuSn and AuSi die attach technologies.PropertyAuSnAuSiSiThermal572715Conductivity (W/m*° K)Thermal360CuZr, Zr = 0.1~180CuW, W = 90Conductivity,weight percentweight percentFlangeResistivity~12−25−20 kΩ *(μΩ * cm)cmEutectic Point (° C.)~280~370CTE (ppm/° C.)1612~4CTE, Flange17CuZr~8CuWCTE for Window20-300Polymers~6(Al2O3)FrameYoung's Modulus59.282.7187 (GPa = 109 N/m2)